Open Silicon Conformance Matrix

The official RISC-V architecture tests, run against 11 open-source cores and compared with the Sail reference model. One agent runs each core; a different agent re-checks every failure before anything is reported.

Cores
11
Tests passed
1596 of 1649 run
No new deviation
7 cores
CoreISA testedPassFailRate*Spec deviations Other failuresSkipped
CV32E40P
97086e95
RV32IMC_Zicsr_Zifencei_Zicntr_Zihpm1201100.0%none1 harness6
CVA6
81245a47
RV64IMAFDCB_Zicsr_Zifencei_Zba_Zbb_Zbc_Zbs_Zcb_Zicond_Zicntr_Zihpm438898.6%6 tests on known issues2 harness385
DarkRISCV
974034aa
RV32I_Zicsr40785.1%2 being verified-560
Hazard3
8af99293
RV32IMAC_Zicsr_Zifencei_Zba_Zbb_Zbc_Zbs_Zcb_Zclsd_Zcmp_Zilsd172797.7%Fixed on develop3 harness, 2 unresolved9
Ibex
af456e25
rv32imc_zicntr_zicsr_zifencei_zihpm1272100.0%none2 harness5
NEORV32
af905649
rv32imacb_zicsr_zifencei_zba_zbb_zbc_zbs_zca_zcb_zcmop_zibi_zicntr_zicond_zihpm_zimop_zmmul_smcntrpmf2132100.0%none2 harness216
PicoRV32
ef203c2b
RV32IMC780100.0%none-529
SERV
f200eb2e
RV32IMCZicsr_Zifencei781188.6%3 new (going to the maintainer first)
Discussed upstream
1 harness, 1 unresolved34
VeeR EL2
0169d669
RV32IMC_Zicsr_Zifencei_Zba_Zbb_Zbc_Zbs145399.3%Reported upstream2 harness883
VeeR EL2 in Caliptra
7b901d59
rv32imc_zicsr_zifencei_zba_zbb_zbc_zbs133498.5%1 being verified2 harness, 1 unresolved894
VexRiscv
baf7dc82
RV32IM_Zicsr_Zifencei52888.1%1 being verified
6 tests on known issues
1 harness27

Run 1, October 2026: riscv-arch-test 4.1.0 (ACT4 tests through a RISCOF adapter), RISCOF 1.25.3, Sail 0.15, Verilator with an Icarus cross-check, each core at the commit shown and in its documented configuration. A harness failure is a problem in our test setup, not in the core, so *Rate leaves those out. Skipped is mostly tests for extensions a core does not claim, plus a few our harness cannot run yet. This is not an official certification. A new deviation is described here only after its maintainer has the report. Updated 10 October 2026, 05:47 UTC.